1. Field of the Invention
The invention relates to a semiconductor memory device and a manufacturing method of the same, and in particular, relates to a semiconductor memory device capable of electrical writing and erasing information and a manufacturing method of the same.
2. Description of the Background Art
EEPROMs (Electrically Erasable Programmable Read Only Memories) have been known as one type of nonvolatile memory semiconductor devices capable of electrically writing and erasing information. The Flash EEPROM is advantageous in that both writing and erasure can be done electrically. However, since two transistors are necessary in the memory cell, it is difficult to realize higher degree of integration. Therefore, a Flash EEPROM has been proposed in which the memory cell includes one transistor, and information charges written therein can be collectively erased electrically. Such a Flash EEPROM is disclosed, for example, in U.S. Pat. No. 4,868,619.
FIG. 106 is a block diagram showing a general structure of a conventional Flash EEPROM. Referring to FIG. 106, the Flash EEPROM includes a memory cell array 330 including a plurality of memory cells (not shown) for storing data arranged in a matrix, a X decoder 331 and a Y decoder 332 for selecting a row and a column of the memory cell array 330 by decoding an external address signal, a Y gate 333, an input/output circuit 335 connected to Y gate 333 for inputting and outputting data, and a control circuit 334 connected to Y gate 333 and to input/output circuit 335 for controlling operation of the Flash EEPROM based on external control signals. X decoder 331, Y decoder 332, Y gate gate 333 control circuit 334, input/output circuit 335 and memory cell array 330 are formed on the same substrate of a semiconductor chip 336. The semiconductor chip 336 is further provided with a power supply input terminal Vcc 337 and a high voltage input terminal Vpp 338.
FIG. 107 is an equivalent circuit diagram showing the schematic structure of the memory cell array 330 shown in FIG. 106. Referring to FIG. 107, in memory cell array 330 a plurality of word lines WL.sub.1, WL.sub.2, . . . , WL.sub.i extended in the row direction and a plurality of bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.i extending in the column direction are arranged crossing orthogonally with each other. Memory cell transistors Q.sub.11, Q.sub.12, . . . Q.sub.ii each having a floating gate are arranged at crossing points of the word lines and the bit lines. Each memory transistor has its drain connected to each bit line. The memory cell transistor has its control gate connected to each word line. The memory cell transistor has its source connected to the source lines SL.sub.1, SL.sub.2, . . . , respectively. The source lines SL.sub.1, SL.sub.2, . . . are connected to source lines S.sub.1, S.sub.2, . . . arranged on both sides.
FIG. 108 is a cross section showing a construction of a memory cell portion of a conventional Flash EEPROM. Referring to FIG. 108, the conventional Flash EEPROM includes a semiconductor substrate 201 as well as a drain impurity diffusion layer 206 and a source impurity diffusion layer 207 which are formed on a main surface of the semiconductor substrate 201 and are spaced from each other by a predetermined distance with a channel region therebetween. The conventional Flash EEPROM further includes a floating gate electrode 203 formed on the channel region with a first gate oxide film 202 therebetween, a control gate electrode 205 formed on the floating gate electrode 203 with an insulating film 204 therebetween, an interlayer thermal oxide film 208 covering the semiconductor substrate 201, floating gate electrode 203 and control gate electrode 205, and an interlayer insulating film 209 covering the interlayer thermal oxide film 208. Gate bird's beak oxide films 210 are formed at opposite ends of the first gate oxide film 202 and opposite ends of the insulating film 204.
The first gate oxide film 202, floating gate electrode 203, insulating film 204, control gate electrode 205, drain impurity diffusion layer 206 and source impurity diffusion layer 207 form basic components of the two-layer gate Flash EEPROM. The interlayer insulating film 209 contains impurity such as boron or phosphorus. The purpose of the interlayer thermal oxide film 208 is to prevent the movement of the impurity such as boron or phosphorus of the interlayer insulating film 209 into the semiconductor substrate 201, control gate electrode 205 or floating gate electrode 203 and thus to prevent change of the electrical characteristics thereof.
Referring to FIG. 108, an operation of the Flash EEPROM will be described below. The Flash EEPROM operates in a write/erase mode for electrically writing or erasing information and also operates in a read mode for reading information. The write/erase mode includes a write mode for electrically writing the information and an erase mode for erasing the information.
In the erase mode, for example, the drain electrode formed of the drain impurity diffusion layer 206 is set in the floating state, and the control gate electrode 205 is set in the grounded state. A high voltage of about 12 V is applied to a source electrode formed of the source impurity diffusion layer 207. Thereby, a Fowler-Nordheim tunnel current flows from the source impurity diffusion layer 207 to the floating gate electrode 203 through the gate bird's beak oxide film 210 at the source side located under the end of the floating gate electrode 203 near the source impurity diffusion layer 207. This Fowler-Nordheim tunnel current is used to draw the electrons from the floating gate electrode 203, whereby the information is erased.
In the write mode, the source impurity diffusion layer 207, i.e., source electrode is grounded. A voltage, e.g., of about 7 V is applied to the drain electrode, i.e., drain impurity diffusion layer 206, and a voltage, e.g., of about 12 V is applied to the control gate electrode 205. In this state, the avalanche phenomenon occurs in the vicinity of the drain impurity diffusion layer 206 under the end of the floating gate electrode 203. Hot electrons, which are generated by the avalanche phenomenon, are implanted into the floating gate electrode 203 through the gate bird's beak oxide film 210 at the drain side from the semiconductor substrate 201, whereby the information is written.
In the read mode, the source impurity diffusion layer 207, i.e., source electrode is grounded. A voltage, e.g., of 1 V is applied to the drain impurity diffusion layer 206, i.e., drain electrode, and a voltage, e.g., of about 3 V is applied to the control gate electrode 205. In this condition, the state of "1" or "0" is determined by the flow or stop of the current from the drain impurity diffusion layer 206 to the source impurity diffusion layer 207. In this manner, the information is read. If electrons exist in the floating gate electrode 203, the current does not flow from the drain impurity diffusion layer 206 to the source impurity diffusion layer 207. As a result, the written state is read. If the electrons have been drawn from the floating gate electrode 203, the current flows from the drain impurity diffusion layer 206 to the source impurity diffusion layer 207, and consequently the erased state is read.
FIGS. 109-118 are cross sections showing a manufacturing process of the conventional Flash EEPROM shown in FIG. 108. Referring to FIGS. 109-118, a manufacturing process of the conventional Flash EEPROM will be described below.
The semiconductor substrate 201 formed of silicon shown in FIG. 109 is subjected to thermal oxidation to form a first gate oxide film layer 202a of about 120 .ANG. in thickness as shown in FIG. 110.
Then, as shown in FIG. 111, a floating gate electrode layer 203a of about 2000 .ANG. in thickness is formed from polysilicon on the first gate oxide film layer 202a.
As shown in FIG. 112, an insulating film layer 204a is formed to a thickness of about 300 .ANG. on the floating gate electrode layer 203a.
As shown in FIG. 113, a control gate electrode layer 205a of polysilicon is formed to a thickness of about 3000 .ANG. on the insulating film layer 204a.
As shown in FIG. 114, photolithography and etching are used to pattern the first gate oxide film layer 202a, floating gate electrode layer 203a, insulating film layer 204a and control gate electrode layer 205a. Thereby, the first gate oxide film 202, floating gate electrode 203, insulating film 204 and control gate electrode 205 are formed.
As shown in FIG. 115, the first gate oxide film 202, floating gate electrode 203, insulating film 204 and control gate electrode 205 are used as a mask, and As (arsenic) ion is implanted into the semiconductor substrate 201 under the condition of about 3.times.10.sup.15 /cm.sup.2. Thereafter, the thermal diffusion technique is used to diffuse the implanted ion, whereby the drain impurity diffusion layer 206 and the source impurity diffusion layer 207 are formed.
As shown in FIG. 116, the interlayer thermal oxide film 208 is formed to cover the semiconductor substrate 201, floating gate electrode 203 and control gate electrode 205.
As shown in FIG. 117, the interlayer insulating film 209 is formed to cover the interlayer thermal oxide film 208. Finally, as shown in FIG. 118, heat treatment by a reflow method is carried out to flatten the interlayer insulating film 209. During this treatment, oxidizer (H.sub.2 O) moves into the interlayer insulating film 209 and interlayer thermal oxide film 208, whereby the gate bird's beak oxide films 210 are formed.
The conventional Flash EEPROM is formed in this manner.
As described above, in the conventional Flash EEPROM, the oxidizer (H.sub.2 O) penetrates the interlayer insulating film 209 and interlayer thermal oxide film 208 during the heat treatment for flattening the interlayer insulating film 209. This causes further oxidization between the semiconductor substrate 201 and the ends of floating gate electrode 203, and between the control gate electrode 205 and the floating gate electrode 203. As a result, the gate bird's beak oxide films 210 are formed. In this manner, the lower end of the floating gate electrode 203 contacts the gate bird's beak oxide films 210, so that the lower end of the floating gate electrode 203 is oxidized to a larger extent as compared with the other portions. If the gate bird's beak oxide films 210 are formed at the lower end of the floating gate 203 near the source impurity diffusion layer 207, the electron is excessively drawn from the floating gate electrode 203 in the data erasing operation, resulting in an over-erased state. If the gate bird's beak oxide films 210 are formed at the end of the floating gate electrode 203 near the drain impurity diffusion layer 206, there is caused a so-called drain disturb phenomenon, in which the electrons are drawn from the floating gate electrode 203 of the unselected memory cell in the data writing operation.
The over-erase phenomenon and drain disturb phenomenon will be described in detail. First, the over-erase phenomenon will be described. In a Flash EEPROM, erasure of all memory cells are carried out at one time and therefore if there is a memory cell through which tunneling current tends to flow easier exists locally, that memory cell is erased earlier than other memory cells. This memory cell which has been erased earlier has electrons therein excessively extracted through the floating gate electrode 203, so that the threshold of the memory cell after erasure becomes negative. This is the so called over-erase phenomenon.
The drain disturbed phenomenon will be described. FIG. 119 is an equivalent circuit diagram explaining the drain disturb phenomenon. Referring to FIG. 119, in a conventional Flash EEPROM, one memory cell includes one transistor, and therefore unlike the conventional EEPROM, there is not a selecting transistor. Therefore, in writing information, write voltage of 7 V is applied to the drain regions of all memory cell transistors connected to same bit line.
More specifically, in the cell selected for writing information, 7 V is applied to the drain region through the bit line BL.sub.1, and 12 V is applied to the control gate through the word line WL.sub.1. At this time, 7 V is applied also to the drain regions of non-selected cells through the bit line BL.sub.1. The non-selected cells with 7 V applied to the drain regions receives 0 V applied to the control gates. At this time, if the non-selected cell is in the written state, electrons have been introduced to the floating gate. More specifically, the potential of the floating gate is at about -3 V. If 7 V is applied to the drain region and 0 V (non-selected state) is applied to the control gate of the non-selected cell in this state, there is generated an electric field as high as 10 MV/cm between the floating gate and the drain region. This causes drain disturb. FIG. 120 is a cross section showing the drain disturb caused by FN tunneling, and FIG. 121 is a cross section showing the drain disturb caused by tunneling between bands.
Referring to FIG. 120, if a high electric field as high as 10 MV/cm is generated between the floating gate electrode 203 and the drain impurity diffusion layer 206, the electrons which have been introduced to the floating gate electrode 203 are extracted to the drain impurity diffused layer 206 because of FN tunneling phenomenon. Consequently, the memory cell is erroneously erased. This is the so called drain disturb caused by FN tunneling.
Referring to FIG. 121, when a high electric field is generated between the floating gate electrode 203 and the drain impurity diffused layer 206, tunneling is generated between bands, resulting in holes. As the generated holes are introduced to the floating gate electrode 203, the same condition as extraction of electrons results. Consequently, the non-selected cell is erroneously erased. This is the so called drain disturb caused by tunneling between bands.
The possible cause of the drain disturb phenomenon and the over-erase phenomenon described above when gate bird's beak oxide films 210 are formed at the lower end portions of the floating gate electrode 203 is as follows. The floating gate electrode 203 is formed of polycrystalline silicon layer. Since the polycrystalline silicon is liable to be oxidized along the grain boundary of the crystal, the shape of the crystal changes from round shape to sharp shape as oxidation proceeds. When the crystal has sharper shape, concentration of electric field tends to occur at the protruding portion. More specifically, at the lower end portions of the floating gate electrode 203 of the prior art, concentration of electric field tends to occur as the gate bird's beak oxide films 210 are formed. Such concentration of electric fields leads to over-erased phenomenon and the drain disturb phenomenon described above.
As described above, if the gate bird's beak oxide films 210 are formed under the lower opposite ends of the floating gate electrode 203, various disadvantages arise.